The present invention generally relates to semiconductor fabrication, and more particularly, to process uniformity control with respect to thermal absorption during fabrication.
Strategic placement of dummy structures in semiconductor design can be used to control process uniformity within a semiconductor wafer. More specifically, dummy structures added to the white space, or non-active regions, of a wafer can be used to control thermal absorption and reduce temperature variations across a wafer during heating techniques used during fabrication. Addition of the dummy structures affects the net thermal conductivity of the entire wafer, in turn affecting the net thermal absorption by the wafer during fabrication.
The dummy structures may typically be integrated into standard process flows and are fabricated adjacent to active devices using similar process techniques used to fabricate the active devices. Because they can be integrated into standard process flows, the dummy structures must be designed to meet uniformity requirements for optimal chemical mechanical polish, epitaxial growth, spacer dielectric deposition, and thermal absorption uniformity. In other words, integrating the dummy structures into standard process flows affect more than just the thermal absorption of the wafer, but can also affect other processing techniques.
As such, the process uniformity strategy has evolved into a complex multi-variable optimization which, due to the number of design levels involved, is often expensive and difficult to validate the alternative optimization strategies on a finished product.